A number of interconnect protocols are in current use. These include Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C), Controller Area Network (CAN) bus, Universal Serial Bus (USB) and “Firewire” serial bus (IEEE1394).
SPI is a three wire, unidirectional (four if bidirectional) interconnection with a unidirectional clock, data, and framing signals. It is low cost but has a low bit rate of less than 1M bits/sec. RF emission is high since each bit transferred generates at least two signal transitions. Tolerance to signal skew is low—less than half a bit time. The ability to address multiple components requires a separate framing signal for each destination.
I2C is a two-wire bidirectional interconnection with bidirectional clock and data signals. It is low cost bus has a low bit rate of less than 500K bits/sec. Like SPI, each bit generates at least two signal transitions and its tolerance to signal skew is low at less than half a bit time. Since signals in I2C are shared and bidirectional, the signal drivers are more complex than SPI. Addressing capability is provided in a header within the packet but the recognition and decoding of the destination requires more logic and power than SPI.
CAN is a two wire interconnect with a single differential, bidirectional data signal. It is low cost but has a low bit rate of less than 1M bits/sec. Each bit can generate as much as two transitions and tolerance to skew of the differential signal is less than half a bit time. Since the signal is shared and bidirectional, the differential signal drivers are more complex than SPI. Since there is no clock signal, bit synchronization must be provided by a local clock that is phase locked to the data signal transitions. This local clock consumes power even during packet transfers for other destinations as well as during idle times. Addressing capability is provided in a header within the packet but the recognition and decoding of the destination requires more logic and power than SPI.
USB is a two wire interconnection with a single differential, bidirectional data signal. It is higher cost but has a high bit rate of up to 480M bits/sec. Each bit can generate as much as two transitions and tolerance to skew of the differential signal is less than half a bit time. Since the signal is shared and bidirectional, the drivers are more complex than SPI. In addition, out-of-band voltages must be detected/sent by the drivers since they are used to signal non-data events like end-of-frame. Like CAN, USB requires a local clock that is phase locked to the signal transitions and which consumes power even during idle time.
IEEE1394 is a four wire interconnection with differential, bidirectional clock and data signals. It is higher cost but has a high bit rate of up to 400M bits/sec. Each bit generates only one transition for low RF emissions and tolerance to signal skew between clock and data is high at almost one bit time. Like USB, IEEE1394 requires a local clock that is phase locked to the clock and data transitions and which consumes power even during idle time.
Ideally, a means of interconnecting functional subsystems embodied within separate components to form a cohesive system would have the following attributes:
High bit rate of at least 10M bits/sec,
Low silicon cost in gates, signal drivers, and pin count,
Low power, especially when idling,
Low RF emissions.
This means of interconnecting would make it possible to mix, match, or replace components in various combinations to create new products or incrementally improve a product. None of the interconnect technologies described above provide all of these attributes.
A fast, inexpensive interconnect would allow the architecture of component designs to be rearranged along boundaries of system functions rather than hardware functions. This would reduce risk by focusing each component design on implementing a group of related functions rather than on implementing and integrating functions, sometimes unrelated, into one component. This, in turn, would also increase the likelihood of component reuse since many related functions are more likely to be useful elsewhere than a collection of unrelated functions.